Global semiconductor foundries are recalibrating multi-year capital expenditure plans as the physics of sub-2nm node manufacturing increase unit costs. Capital allocation is noticeably pivoting toward advanced 2.5D and 3D packaging technologies to sustain performance gains.
Packaging as the New Scaling Frontier
With extreme ultraviolet lithography costs rising exponentially, chip designers are increasingly utilizing chiplet architectures. Heterogeneous integration allows vendors to combine mature, high-yield process nodes with specialized compute dies, mitigating overall wafer cost inflation.